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authorBrian Cully <bjc@kublai.com>2019-09-23 12:45:09 -0400
committerBrian Cully <bjc@kublai.com>2019-09-24 10:55:25 -0400
commitfcc6951c707144ba423b81e03bc2f34b6cfa7286 (patch)
tree574f64eb11e23920343137e352eb1279f1940a5d /src/pipe/status_bk.rs
parent77d1fdf044326cfb039728bf94a998f1dd1e8d1e (diff)
downloadatsamd-usb-host-fcc6951c707144ba423b81e03bc2f34b6cfa7286.tar.gz
atsamd-usb-host-fcc6951c707144ba423b81e03bc2f34b6cfa7286.zip
Mark pipe descriptor register memory as volatile.
Most of the values in the descriptor memory can be modified by the hardware, so we need to tell Rust that. Also, refactor the common register setup code into `register.rs`.
Diffstat (limited to 'src/pipe/status_bk.rs')
-rw-r--r--src/pipe/status_bk.rs56
1 files changed, 12 insertions, 44 deletions
diff --git a/src/pipe/status_bk.rs b/src/pipe/status_bk.rs
index 50a549c..892da96 100644
--- a/src/pipe/status_bk.rs
+++ b/src/pipe/status_bk.rs
@@ -1,48 +1,22 @@
+use super::register::{Readable, Register, Writable, R as GenR, W as GenW};
+
/// ยง32.8.7.5
/// Host Status Bank.
///
/// Offset: 0x0a & 0x1a
/// Reset: 0xxxxxxx
/// Property: NA
-#[derive(Clone, Copy, Debug)]
-#[repr(C, packed)]
-pub(crate) struct StatusBk(u8);
-
-pub(crate) struct R {
- bits: u8,
-}
-pub(crate) struct W {
- bits: u8,
-}
+pub type StatusBk = Register<u8, _StatusBk>;
+impl Readable for StatusBk {}
+impl Writable for StatusBk {}
-impl StatusBk {
- pub fn read(self) -> R {
- R { bits: self.0 }
- }
-
- pub fn write<F>(&mut self, f: F)
- where
- F: FnOnce(&mut W) -> &mut W,
- {
- let mut w = W { bits: self.0 };
- f(&mut w);
- self.0 = w.bits;
- }
-}
+pub type R = GenR<u8, StatusBk>;
+pub type W = GenW<u8, StatusBk>;
-impl From<u8> for StatusBk {
- fn from(v: u8) -> Self {
- Self(v)
- }
-}
+pub struct _StatusBk;
impl R {
- /// Value in raw bits.
- pub fn bits(&self) -> u8 {
- self.bits
- }
-
pub fn errorflow(&self) -> ErrorFlowR {
let bits = {
const POS: u8 = 1;
@@ -75,7 +49,7 @@ impl R {
/// transfer, a NAK handshake has been received. For Isochronous IN
/// transfer, an overrun condition has occurred. For Isochronous OUT
/// transfer, an underflow condition has occurred.
-pub(crate) struct ErrorFlowR(bool);
+pub struct ErrorFlowR(bool);
impl ErrorFlowR {
pub fn bit(&self) -> bool {
self.0
@@ -96,7 +70,7 @@ impl ErrorFlowR {
///
/// This bit is set when a CRC error has been detected in an
/// isochronous IN endpoint bank.
-pub(crate) struct CRCErrR(bool);
+pub struct CRCErrR(bool);
impl CRCErrR {
pub fn bit(&self) -> bool {
self.0
@@ -112,12 +86,6 @@ impl CRCErrR {
}
impl W {
- /// Write raw bits.
- pub unsafe fn bits(&mut self, v: u8) -> &mut Self {
- self.bits = v;
- self
- }
-
pub fn errorflow(&mut self) -> ErrorFlowW {
ErrorFlowW { w: self }
}
@@ -127,7 +95,7 @@ impl W {
}
}
-pub(crate) struct ErrorFlowW<'a> {
+pub struct ErrorFlowW<'a> {
w: &'a mut W,
}
impl<'a> ErrorFlowW<'a> {
@@ -148,7 +116,7 @@ impl<'a> ErrorFlowW<'a> {
}
}
-pub(crate) struct CRCErrW<'a> {
+pub struct CRCErrW<'a> {
w: &'a mut W,
}
impl<'a> CRCErrW<'a> {