From c2d0f2af2f21a3c9539b89749bf6139c9f15b903 Mon Sep 17 00:00:00 2001 From: Brian Cully Date: Sat, 10 Aug 2019 19:40:34 -0400 Subject: A bunch of cleanup and fixes. Simplify the code a bunch to reduce it to states we actually care about. This will now probe my Logitech G105, NIZ Plum 85EC, and Keyboard.io Model 01. * Don't listen for wakeup interrupts. Only listen for device connection and disconnection, which wakeups sometimes mean. * Remove the SETTLE_DELAY stuff on device connection, as this appears to be handled in hardware, and prevents over-delay which was causing the Model 01 to reset, since it wasn't getting a SOF in time. * Set initial max packet size for address 0 endpoint 0 based on whether the connection is Full Speed or Low Speed. * Remove all intflag checks from USB handler that we don't explicitly set up. * Always listen dor dconn/ddisc in handler. Since we're using a ring buffer for event storage, we shouldn't miss these and always handle them in order. * Don't freeze pipes on errors. Let the hardware do it. * Don't retransmit packets on errors, just keep polling hardware. * Move trfail check to the end, since it's either dependent on previous, more specific checks, or it's just a NAK (but, for some reason, not ERRORFLOW). * Add `modify` method to control pipe register. --- src/pipe.rs | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) (limited to 'src/pipe.rs') diff --git a/src/pipe.rs b/src/pipe.rs index e90b88b..7d8a4b7 100644 --- a/src/pipe.rs +++ b/src/pipe.rs @@ -420,8 +420,6 @@ impl Pipe<'_, '_> { naks += 1; if naks > retries { break; - } else { - self.dispatch_packet(ep, token); } } } @@ -481,27 +479,23 @@ impl Pipe<'_, '_> { if self.is_transfer_complete(token)? { self.regs.statusset.write(|w| w.pfreeze().set_bit()); Ok(true) - } else if self.regs.intflag.read().trfail().bit_is_set() { - self.regs.intflag.write(|w| w.trfail().set_bit()); - trace!("trfail"); - self.regs.statusset.write(|w| w.pfreeze().set_bit()); - self.log_regs(); - Err(PipeErr::TransferFail) } else if self.desc.bank0.status_bk.read().errorflow().bit_is_set() { trace!("errorflow"); - self.regs.statusset.write(|w| w.pfreeze().set_bit()); self.log_regs(); Err(PipeErr::Flow) } else if self.desc.bank0.status_pipe.read().touter().bit_is_set() { trace!("touter"); - self.regs.statusset.write(|w| w.pfreeze().set_bit()); self.log_regs(); Err(PipeErr::HWTimeout) } else if self.desc.bank0.status_pipe.read().dtgler().bit_is_set() { trace!("dtgler"); - self.regs.statusset.write(|w| w.pfreeze().set_bit()); self.log_regs(); Err(PipeErr::DataToggle) + } else if self.regs.intflag.read().trfail().bit_is_set() { + self.regs.intflag.write(|w| w.trfail().set_bit()); + trace!("trfail"); + self.log_regs(); + Err(PipeErr::TransferFail) } else { // Nothing wrong, but not done yet. Ok(false) -- cgit v1.2.3