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| author | Brian Cully <bjc@kublai.com> | 2019-07-28 11:51:29 -0400 |
|---|---|---|
| committer | Brian Cully <bjc@kublai.com> | 2019-07-28 11:51:59 -0400 |
| commit | d5927616c9fa4feb4cf819c81e26536ca97b1c4e (patch) | |
| tree | 64ba5f043eb426fa9149b05ba16d8a193237ced7 /usbh/src/pipe/addr.rs | |
| parent | ea0e5159d78840f91490c78c1b8b569539fc0185 (diff) | |
| download | samd21-demo-d5927616c9fa4feb4cf819c81e26536ca97b1c4e.tar.gz samd21-demo-d5927616c9fa4feb4cf819c81e26536ca97b1c4e.zip | |
Put word-aligned assert back in addr reg.
Diffstat (limited to 'usbh/src/pipe/addr.rs')
| -rw-r--r-- | usbh/src/pipe/addr.rs | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/usbh/src/pipe/addr.rs b/usbh/src/pipe/addr.rs index 98199d1..81cef5d 100644 --- a/usbh/src/pipe/addr.rs +++ b/usbh/src/pipe/addr.rs @@ -89,8 +89,7 @@ impl<'a> AddrW<'a> { pub unsafe fn bits(self, v: u32) -> &'a mut W { // Address must be 32-bit aligned. cf ยง32.8.7.2 of SAMD21 data // sheet. - - //assert!((v & 0x3) == 0); + assert!((v & 0x3) == 0); self.w.bits = v; self.w } |