diff options
| -rw-r--r-- | usbh/src/pipe.rs | 71 |
1 files changed, 37 insertions, 34 deletions
diff --git a/usbh/src/pipe.rs b/usbh/src/pipe.rs index 8644dee..f442873 100644 --- a/usbh/src/pipe.rs +++ b/usbh/src/pipe.rs @@ -290,6 +290,9 @@ impl Pipe<'_, '_> { } } + // This and `dispatch_result` are the only function that calls + // `millis`. If we can make this just take the current timestamp, + // we can make this non-blocking. pub(crate) fn dispatch_retries( &mut self, token: USBToken, @@ -321,40 +324,6 @@ impl Pipe<'_, '_> { last_result } - fn log_regs(&self) { - // Pipe regs - let cfg = self.regs.cfg.read().bits(); - let bin = self.regs.binterval.read().bits(); - let sts = self.regs.status.read().bits(); - let ifl = self.regs.intflag.read().bits(); - trace!( - "p{}: cfg: {:x}, bin: {:x}, sts: {:x}, ifl: {:x}", - self.num, - cfg, - bin, - sts, - ifl - ); - - // Pipe RAM regs - let adr = self.desc.bank0.addr.read().bits(); - let pks = self.desc.bank0.pcksize.read().bits(); - let ext = self.desc.bank0.extreg.read().bits(); - let sbk = self.desc.bank0.status_bk.read().bits(); - let hcp = self.desc.bank0.ctrl_pipe.read().bits(); - let spi = self.desc.bank0.status_pipe.read().bits(); - trace!( - "p{}: adr: {:x}, pks: {:x}, ext: {:x}, sbk: {:x}, hcp: {:x}, spi: {:x}", - self.num, - adr, - pks, - ext, - sbk, - hcp, - spi - ); - } - fn dispatch_packet(&mut self, token: USBToken) { self.regs .cfg @@ -456,6 +425,40 @@ impl Pipe<'_, '_> { _ => Err(PipeErr::InvalidToken), } } + + fn log_regs(&self) { + // Pipe regs + let cfg = self.regs.cfg.read().bits(); + let bin = self.regs.binterval.read().bits(); + let sts = self.regs.status.read().bits(); + let ifl = self.regs.intflag.read().bits(); + trace!( + "p{}: cfg: {:x}, bin: {:x}, sts: {:x}, ifl: {:x}", + self.num, + cfg, + bin, + sts, + ifl + ); + + // Pipe RAM regs + let adr = self.desc.bank0.addr.read().bits(); + let pks = self.desc.bank0.pcksize.read().bits(); + let ext = self.desc.bank0.extreg.read().bits(); + let sbk = self.desc.bank0.status_bk.read().bits(); + let hcp = self.desc.bank0.ctrl_pipe.read().bits(); + let spi = self.desc.bank0.status_pipe.read().bits(); + trace!( + "p{}: adr: {:x}, pks: {:x}, ext: {:x}, sbk: {:x}, hcp: {:x}, spi: {:x}", + self.num, + adr, + pks, + ext, + sbk, + hcp, + spi + ); + } } #[derive(Copy, Clone, Debug, PartialEq)] |