diff options
| -rw-r--r-- | usbh/src/pipe.rs | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/usbh/src/pipe.rs b/usbh/src/pipe.rs index be4ca57..8644dee 100644 --- a/usbh/src/pipe.rs +++ b/usbh/src/pipe.rs @@ -202,7 +202,7 @@ impl Pipe<'_, '_> { buf: &DataBuf, nak_limit: usize, millis: &dyn Fn() -> usize, - ) -> Result<(), PipeErr> { + ) -> Result<(usize), PipeErr> { // Data needs to be word aligned. assert!((buf.ptr as u32) & 0x3 == 0); // byte_count section of register is 14 bits. @@ -247,30 +247,24 @@ impl Pipe<'_, '_> { } //self.dtgl(); + self.regs.statusset.write(|w| w.pfreeze().set_bit()); if bytes_received < buf.len { self.log_regs(); // TODO: honestly, this is probably a panic condition, // since whatever's in DataBuf.ptr is totally // invalid. Alternately, this function should be declared // `unsafe`. - self.regs.statusset.write(|w| w.pfreeze().set_bit()); Err(PipeErr::ShortPacket) } else { - self.regs.statusset.write(|w| w.pfreeze().set_bit()); - Ok(()) + Ok(bytes_received) } } - // TODO: these two functions shouldn't be exposed, since they're - // pretty hardware-dependent. Instead, move USBHost.control_req() - // into this module (where it will sit with its peers - // `in_transfer` and `out_transfer`) and combine it with `send` - // (which is its only use). - pub(crate) fn dtgl_set(&mut self) { + fn dtgl_set(&mut self) { self.regs.statusset.write(|w| w.dtgl().set_bit()); } - pub(crate) fn dtgl_clear(&mut self) { + fn dtgl_clear(&mut self) { self.regs.statusclr.write(|w| unsafe { // No function for this. FIXME: need to patch the SVD for // PSTATUSCLR.DTGL at bit0. No? This is in the SVD, but |