1 files changed, 18 insertions, 28 deletions

diff --git a/app/src/usb/pipe.rs b/app/src/usb/pipe.rs
index 12ca4cb..908c8e5 100644
--- a/app/src/usb/pipe.rs
+++ b/app/src/usb/pipe.rs
@@ -12,10 +12,10 @@ use pck_size::PckSize;
 use status_bk::StatusBk;
 use status_pipe::StatusPipe;
 
-use crate::logln_now;
 use crate::rtc;
 
 use core::convert::TryInto;
+use log::info;
 
 // FIXME: this stuff is needed for PipeRegs, and while tied to samd,
 // it shouldn't be tied to trinket_m0. Will need to figure out a
@@ -70,13 +70,13 @@ impl PipeTable {
         let pregs = PipeRegs::from(host, i);
         let pdesc = &mut self.tbl[i];
 
-        logln_now!("setting paddr of pipe {} to {}:{}", i, addr, ep);
-        logln_now!("cpipe0: {:x}", pdesc.bank0.ctrl_pipe.read().bits());
+        info!("setting paddr of pipe {} to {}:{}", i, addr, ep);
+        info!("cpipe0: {:x}", pdesc.bank0.ctrl_pipe.read().bits());
         pdesc.bank0.ctrl_pipe.write(|w| {
             w.pdaddr().set_addr(addr);
             w.pepnum().set_epnum(ep)
         });
-        logln_now!("cpipe1: {:x}", pdesc.bank0.ctrl_pipe.read().bits());
+        info!("cpipe1: {:x}", pdesc.bank0.ctrl_pipe.read().bits());
         Pipe {
             num: i,
             regs: pregs,
@@ -103,7 +103,7 @@ impl Pipe<'_, '_> {
         // byte_count section of register is 14 bits.
         assert!(buf.len < 16_384);
 
-        logln_now!("p{}: sending {:?}", self.num, buf);
+        info!("p{}: sending {:?}", self.num, buf);
 
         // Equiv to UHD_Pipe_Write(epAddr: 0, sizeof(setup_packet), &setup_packet)
         self.desc
@@ -129,7 +129,7 @@ impl Pipe<'_, '_> {
         // byte_count section of register is 14 bits.
         assert!(buf.len < 16_384);
 
-        logln_now!("p{}: Should IN for {}b.", self.num, buf.len);
+        info!("p{}: Should IN for {}b.", self.num, buf.len);
         // TODO: should just pass pipe and pregs in, probably.  TODO:
         // merge with stuff in `send_to_pipe` that also does this.
         self.desc
@@ -162,14 +162,14 @@ impl Pipe<'_, '_> {
     ) -> Result<(), PipeErr> {
         assert!(retries > 0);
 
-        logln_now!("initial regs");
+        info!("initial regs");
         self.log_regs();
 
         let until = rtc::millis() + USB_TIMEOUT;
         let mut last_result: Result<(), PipeErr> = Err(PipeErr::SWTimeout);
         let mut naks = 0;
         while naks <= retries {
-            logln_now!("p{}: dispatch {:?} retry {}", self.num, token, naks);
+            info!("p{}: dispatch {:?} retry {}", self.num, token, naks);
 
             self.dispatch_packet(token);
             last_result = self.dispatch_result(token, until);
@@ -201,13 +201,9 @@ impl Pipe<'_, '_> {
         let bin = self.regs.binterval.read().bits();
         let sts = self.regs.status.read().bits();
         let ifl = self.regs.intflag.read().bits();
-        logln_now!(
+        info!(
             "p{}: cfg: {:x}, bin: {:x}, sts: {:x}, ifl: {:x}",
-            self.num,
-            cfg,
-            bin,
-            sts,
-            ifl
+            self.num, cfg, bin, sts, ifl
         );
 
         // Pipe RAM regs
@@ -217,15 +213,9 @@ impl Pipe<'_, '_> {
         let sbk = self.desc.bank0.status_bk.read().bits();
         let hcp = self.desc.bank0.ctrl_pipe.read().bits();
         let spi = self.desc.bank0.status_pipe.read().bits();
-        logln_now!(
+        info!(
             "p{}: adr: {:x}, pks: {:x}, ext: {:x}, sbk: {:x}, hcp: {:x}, spi: {:x}",
-            self.num,
-            adr,
-            pks,
-            ext,
-            sbk,
-            hcp,
-            spi
+            self.num, adr, pks, ext, sbk, hcp, spi
         );
     }
 
@@ -253,17 +243,17 @@ impl Pipe<'_, '_> {
             if self.is_transfer_complete(token)? {
                 return Ok(());
             } else if self.regs.intflag.read().stall().bit_is_set() {
-                logln_now!("stall");
+                info!("stall");
                 self.log_regs();
                 self.regs.intflag.write(|w| w.stall().set_bit());
                 return Err(PipeErr::Stall);
             } else if self.regs.intflag.read().trfail().bit_is_set() {
-                logln_now!("trfail");
+                info!("trfail");
                 self.log_regs();
                 self.regs.intflag.write(|w| w.trfail().set_bit());
                 return Err(PipeErr::TransferFail);
             } else if self.desc.bank0.status_bk.read().errorflow().bit_is_set() {
-                logln_now!("errorflow");
+                info!("errorflow");
                 self.log_regs();
                 self.desc
                     .bank0
@@ -271,7 +261,7 @@ impl Pipe<'_, '_> {
                     .write(|w| w.errorflow().clear_bit());
                 return Err(PipeErr::Flow);
             } else if self.desc.bank0.status_pipe.read().touter().bit_is_set() {
-                logln_now!("touter");
+                info!("touter");
                 self.log_regs();
                 self.desc
                     .bank0
@@ -279,7 +269,7 @@ impl Pipe<'_, '_> {
                     .write(|w| w.touter().clear_bit());
                 return Err(PipeErr::HWTimeout);
             } else if self.desc.bank0.status_pipe.read().dtgler().bit_is_set() {
-                logln_now!("dtgler");
+                info!("dtgler");
                 self.log_regs();
                 self.desc
                     .bank0
@@ -288,7 +278,7 @@ impl Pipe<'_, '_> {
                 return Err(PipeErr::DataToggle);
             }
         }
-        logln_now!("swtimeout");
+        info!("swtimeout");
         self.log_regs();
         Err(PipeErr::SWTimeout)
     }