1 files changed, 27 insertions, 19 deletions

diff --git a/usbh/src/pipe.rs b/usbh/src/pipe.rs
index d880d7a..833ddea 100644
--- a/usbh/src/pipe.rs
+++ b/usbh/src/pipe.rs
@@ -13,7 +13,7 @@ use status_bk::StatusBk;
 use status_pipe::StatusPipe;
 
 use core::convert::TryInto;
-use log::info;
+use log::trace;
 
 use atsamd_hal::target_device::usb::{
     self,
@@ -65,13 +65,11 @@ impl PipeTable {
         let pregs = PipeRegs::from(host, i);
         let pdesc = &mut self.tbl[i];
 
-        info!("setting paddr of pipe {} to {}:{}", i, addr, ep);
-        info!("cpipe0: {:x}", pdesc.bank0.ctrl_pipe.read().bits());
+        trace!("setting paddr of pipe {} to {}:{}", i, addr, ep);
         pdesc.bank0.ctrl_pipe.write(|w| {
             w.pdaddr().set_addr(addr);
             w.pepnum().set_epnum(ep)
         });
-        info!("cpipe1: {:x}", pdesc.bank0.ctrl_pipe.read().bits());
         Pipe {
             num: i,
             regs: pregs,
@@ -99,7 +97,7 @@ impl Pipe<'_, '_> {
         // byte_count section of register is 14 bits.
         assert!(buf.len < 16_384);
 
-        info!("p{}: sending {:?}", self.num, buf);
+        trace!("p{}: sending {:?}", self.num, buf);
 
         self.desc
             .bank0
@@ -125,7 +123,7 @@ impl Pipe<'_, '_> {
         // byte_count section of register is 14 bits.
         assert!(buf.len < 16_384);
 
-        info!("p{}: Should IN for {}b.", self.num, buf.len);
+        trace!("p{}: Should IN for {}b.", self.num, buf.len);
         self.desc.bank0.pcksize.write(|w| {
             unsafe { w.byte_count().bits(buf.len as u16) };
             unsafe { w.multi_packet_size().bits(0) }
@@ -146,7 +144,7 @@ impl Pipe<'_, '_> {
             self.dispatch_retries(USBToken::In, nak_limit, millis)?;
             bytes_received += self.desc.bank0.pcksize.read().byte_count().bits() as usize;
             assert!(bytes_received <= buf.len);
-            info!("!! read {} of {}", bytes_received, buf.len);
+            trace!("!! read {} of {}", bytes_received, buf.len);
         }
         self.regs.statusset.write(|w| w.pfreeze().set_bit());
 
@@ -169,14 +167,14 @@ impl Pipe<'_, '_> {
     ) -> Result<(), PipeErr> {
         assert!(retries > 0);
 
-        info!("initial regs");
+        trace!("initial regs");
         self.log_regs();
 
         let until = millis() + USB_TIMEOUT;
         let mut last_result: Result<(), PipeErr> = Err(PipeErr::SWTimeout);
         let mut naks = 0;
         while naks <= retries {
-            info!("p{}: dispatch {:?} retry {}", self.num, token, naks);
+            trace!("p{}: dispatch {:?} retry {}", self.num, token, naks);
 
             self.dispatch_packet(token);
             last_result = self.dispatch_result(token, until, millis);
@@ -208,9 +206,13 @@ impl Pipe<'_, '_> {
         let bin = self.regs.binterval.read().bits();
         let sts = self.regs.status.read().bits();
         let ifl = self.regs.intflag.read().bits();
-        info!(
+        trace!(
             "p{}: cfg: {:x}, bin: {:x}, sts: {:x}, ifl: {:x}",
-            self.num, cfg, bin, sts, ifl
+            self.num,
+            cfg,
+            bin,
+            sts,
+            ifl
         );
 
         // Pipe RAM regs
@@ -220,9 +222,15 @@ impl Pipe<'_, '_> {
         let sbk = self.desc.bank0.status_bk.read().bits();
         let hcp = self.desc.bank0.ctrl_pipe.read().bits();
         let spi = self.desc.bank0.status_pipe.read().bits();
-        info!(
+        trace!(
             "p{}: adr: {:x}, pks: {:x}, ext: {:x}, sbk: {:x}, hcp: {:x}, spi: {:x}",
-            self.num, adr, pks, ext, sbk, hcp, spi
+            self.num,
+            adr,
+            pks,
+            ext,
+            sbk,
+            hcp,
+            spi
         );
     }
 
@@ -255,17 +263,17 @@ impl Pipe<'_, '_> {
             if self.is_transfer_complete(token)? {
                 return Ok(());
             } else if self.regs.intflag.read().stall().bit_is_set() {
-                info!("stall");
+                trace!("stall");
                 self.log_regs();
                 self.regs.intflag.write(|w| w.stall().set_bit());
                 return Err(PipeErr::Stall);
             } else if self.regs.intflag.read().trfail().bit_is_set() {
-                info!("trfail");
+                trace!("trfail");
                 self.log_regs();
                 self.regs.intflag.write(|w| w.trfail().set_bit());
                 return Err(PipeErr::TransferFail);
             } else if self.desc.bank0.status_bk.read().errorflow().bit_is_set() {
-                info!("errorflow");
+                trace!("errorflow");
                 self.log_regs();
                 self.desc
                     .bank0
@@ -273,7 +281,7 @@ impl Pipe<'_, '_> {
                     .write(|w| w.errorflow().clear_bit());
                 return Err(PipeErr::Flow);
             } else if self.desc.bank0.status_pipe.read().touter().bit_is_set() {
-                info!("touter");
+                trace!("touter");
                 self.log_regs();
                 self.desc
                     .bank0
@@ -281,7 +289,7 @@ impl Pipe<'_, '_> {
                     .write(|w| w.touter().clear_bit());
                 return Err(PipeErr::HWTimeout);
             } else if self.desc.bank0.status_pipe.read().dtgler().bit_is_set() {
-                info!("dtgler");
+                trace!("dtgler");
                 self.log_regs();
                 self.desc
                     .bank0
@@ -290,7 +298,7 @@ impl Pipe<'_, '_> {
                 return Err(PipeErr::DataToggle);
             }
         }
-        info!("swtimeout");
+        trace!("swtimeout");
         self.log_regs();
         Err(PipeErr::SWTimeout)
     }