diff options
Diffstat (limited to 'usbh/src/pipe.rs')
-rw-r--r-- | usbh/src/pipe.rs | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/usbh/src/pipe.rs b/usbh/src/pipe.rs index e17bec5..936aa23 100644 --- a/usbh/src/pipe.rs +++ b/usbh/src/pipe.rs @@ -92,8 +92,8 @@ pub(crate) struct Pipe<'a, 'b> { impl Pipe<'_, '_> { pub(crate) fn control_req( &mut self, - bm_request_type: BMRequestType, - b_request: USBRequest, + bm_request_type: RequestType, + b_request: RequestCode, w_value: WValue, w_index: u16, buf: Option<DataBuf>, @@ -110,7 +110,7 @@ impl Pipe<'_, '_> { /* * Setup stage. */ - let mut setup_packet = USBSetupPacket { + let mut setup_packet = SetupPacket { bm_request_type: bm_request_type, b_request: b_request, w_value: w_value, @@ -133,6 +133,8 @@ impl Pipe<'_, '_> { */ self.dtgl_set(); if let Some(b) = buf { + // TODO: data stage, has up to 5,000ms (in 500ms + // per-packet chunks) to complete. cf §9.2.6.4 of USB 2.0. match bm_request_type.direction() { USBSetupDirection::DeviceToHost => { trace!("buf0: {:?}", &b); @@ -149,6 +151,8 @@ impl Pipe<'_, '_> { /* * Status stage. */ + // TODO: status stage has up to 50ms to complete. cf §9.2.6.4 + // of USB 2.0. self.dtgl_set(); self.desc.bank0.pcksize.write(|w| { unsafe { w.byte_count().bits(0) }; |