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-rw-r--r--usbh/src/pipe.rs9
1 files changed, 0 insertions, 9 deletions
diff --git a/usbh/src/pipe.rs b/usbh/src/pipe.rs
index c6f2023..4910c3e 100644
--- a/usbh/src/pipe.rs
+++ b/usbh/src/pipe.rs
@@ -154,10 +154,6 @@ impl Pipe<'_, '_> {
unsafe { w.multi_packet_size().bits(0) }
});
- // PSTATUSSET.DTGL set -- TODO: figure out if this is
- // necessary.
- self.regs.statusset.write(|w| w.dtgl().set_bit());
-
let token = match bm_request_type.direction() {
USBSetupDirection::DeviceToHost => USBToken::Out,
USBSetupDirection::HostToDevice => USBToken::In,
@@ -203,11 +199,6 @@ impl Pipe<'_, '_> {
nak_limit: usize,
millis: &dyn Fn() -> usize,
) -> Result<(usize), PipeErr> {
- // Data needs to be word aligned.
- assert!((buf.ptr as u32) & 0x3 == 0);
- // byte_count section of register is 14 bits.
- assert!(buf.len < 16_384);
-
// TODO: pull this from pipe descriptor for this addr/ep.
let packet_size = 8;