aboutsummaryrefslogtreecommitdiffstats
path: root/usbh/src/pipe/status_bk.rs
blob: 489fc625061296d7ed7a3b245000587964e90a7c (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
/// §32.8.7.5
/// Host Status Bank.
///
/// Offset: 0x0a & 0x1a
/// Reset: 0xxxxxxx
/// Property: NA
#[derive(Clone, Copy, Debug)]
#[repr(C, packed)]
pub(crate) struct StatusBk(u8);

pub(crate) struct R {
    bits: u8,
}

pub(crate) struct W {
    bits: u8,
}

impl StatusBk {
    pub fn read(&self) -> R {
        R { bits: self.0 }
    }

    pub fn write<F>(&mut self, f: F)
    where
        F: FnOnce(&mut W) -> &mut W,
    {
        let mut w = W { bits: self.0 };
        f(&mut w);
        self.0 = w.bits;
    }
}

impl From<u8> for StatusBk {
    fn from(v: u8) -> Self {
        Self(v)
    }
}

impl R {
    /// Value in raw bits.
    pub fn bits(&self) -> u8 {
        self.bits
    }

    pub fn errorflow(&self) -> ErrorFlowR {
        let bits = {
            const POS: u8 = 1;
            const MASK: u8 = 1;
            ((self.bits >> POS) & MASK) == 1
        };

        ErrorFlowR(bits)
    }

    pub fn crcerr(&self) -> CRCErrR {
        let bits = {
            const POS: u8 = 0;
            const MASK: u8 = 1;
            ((self.bits >> POS) & MASK) == 1
        };

        CRCErrR(bits)
    }
}

/// Error Flow Status
///
/// This bit defines the Error Flow Status.
///
/// This bit is set when a Error Flow has been detected during
/// transfer from/towards this bank.
///
/// For IN transfer, a NAK handshake has been received. For OUT
/// transfer, a NAK handshake has been received. For Isochronous IN
/// transfer, an overrun condition has occurred. For Isochronous OUT
/// transfer, an underflow condition has occurred.
pub(crate) struct ErrorFlowR(bool);
impl ErrorFlowR {
    pub fn bit(&self) -> bool {
        self.0
    }

    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }

    pub fn bit_is_clear(&self) -> bool {
        !self.bit_is_set()
    }
}

/// CRC Error
///
/// This bit defines the CRC Error Status.
///
/// This bit is set when a CRC error has been detected in an
/// isochronous IN endpoint bank.
pub(crate) struct CRCErrR(bool);
impl CRCErrR {
    pub fn bit(&self) -> bool {
        self.0
    }

    pub fn bit_is_set(&self) -> bool {
        self.bit()
    }

    pub fn bit_is_clear(&self) -> bool {
        !self.bit_is_set()
    }
}

impl W {
    /// Write raw bits.
    pub unsafe fn bits(&mut self, v: u8) -> &mut Self {
        self.bits = v;
        self
    }

    pub fn errorflow(&mut self) -> ErrorFlowW {
        ErrorFlowW { w: self }
    }

    pub fn crcerr(&mut self) -> CRCErrW {
        CRCErrW { w: self }
    }
}

pub(crate) struct ErrorFlowW<'a> {
    w: &'a mut W,
}
impl<'a> ErrorFlowW<'a> {
    pub fn bit(self, v: bool) -> &'a mut W {
        const POS: u8 = 1;
        const MASK: bool = true;
        self.w.bits &= !((MASK as u8) << POS);
        self.w.bits |= ((v & MASK) as u8) << POS;
        self.w
    }

    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }

    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
}

pub(crate) struct CRCErrW<'a> {
    w: &'a mut W,
}
impl<'a> CRCErrW<'a> {
    pub fn bit(self, v: bool) -> &'a mut W {
        const POS: u8 = 0;
        const MASK: bool = true;
        self.w.bits &= !((MASK as u8) << POS);
        self.w.bits |= ((v & MASK) as u8) << POS;
        self.w
    }

    pub fn set_bit(self) -> &'a mut W {
        self.bit(true)
    }

    pub fn clear_bit(self) -> &'a mut W {
        self.bit(false)
    }
}