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authorBrian Cully <bjc@kublai.com>2019-08-15 20:44:51 -0400
committerBrian Cully <bjc@kublai.com>2019-08-15 20:44:51 -0400
commitda405029113f9c188313b9477f4dc13aa3ab52f9 (patch)
tree058dcca7068d597e572112f0c182fd3b701a9d59 /ble/src/uarte1.rs
parent101a0859612cbf40364d198eea60b9ae934f721a (diff)
downloadbleusb-da405029113f9c188313b9477f4dc13aa3ab52f9.tar.gz
bleusb-da405029113f9c188313b9477f4dc13aa3ab52f9.zip
More WIP for btle comms.
Diffstat (limited to 'ble/src/uarte1.rs')
-rw-r--r--ble/src/uarte1.rs52
1 files changed, 18 insertions, 34 deletions
diff --git a/ble/src/uarte1.rs b/ble/src/uarte1.rs
index 1afce29..0beb8cd 100644
--- a/ble/src/uarte1.rs
+++ b/ble/src/uarte1.rs
@@ -2,9 +2,9 @@ use log::info;
use nrf52840_hal::uarte::{self, Uarte};
use starb::{Reader, RingBuffer, Writer};
-static mut RB: RingBuffer<u8> = RingBuffer::new(0);
+static mut RB: RingBuffer<u8> = RingBuffer::new();
-const BUFLEN: usize = 128;
+const BUFLEN: usize = 255;
struct DoubleBuffer {
bank0: [u8; BUFLEN],
@@ -51,6 +51,9 @@ where
w.rxstarted().set_bit()
});
+ // Keep the transmission going constantly.
+ uarte.0.shorts.write(|w| w.endrx_startrx().set_bit());
+
let ptr = unsafe { DBL_BUFF.next_ptr() };
info!("setting up dma: p: {:x}, maxcnt: {}", ptr as u32, BUFLEN);
uarte.0.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
@@ -75,48 +78,29 @@ where
if uarte.0.events_endrx.read().events_endrx().bit_is_set() {
uarte.0.events_endrx.write(|w| w.events_endrx().clear_bit());
- // The buffer should be swapped from the RXSTARTED event, so
- // we can restart the read immediately.
- let optr = uarte.0.rxd.ptr.read().ptr().bits();
- let ptr = unsafe { DBL_BUFF.cur_ptr() as u32 };
- /*
- if optr == ptr {
- uarte
- .0
- .rxd
- .ptr
- .write(|w| unsafe { w.ptr().bits(DBL_BUFF.next_ptr() as _) });
- }
- */
- uarte.0.tasks_startrx.write(|w| w.tasks_startrx().set_bit());
-
// Copy DMA buffer to ring buffer.
let len = uarte.0.rxd.amount.read().amount().bits();
+ let ptr = unsafe { DBL_BUFF.cur_ptr() };
+ /*
+ let optr = uarte.0.rxd.ptr.read().ptr().bits();
let mc = uarte.0.rxd.maxcnt.read().maxcnt().bits();
info!(
- "endrx - l: {}, p: {:x}, mc: {}, b: {:x}",
- len, optr, mc, ptr
+ "ENDRX optr: {:x}, mc: {}, ptr: {:x}, len: {}",
+ optr, mc, ptr as u32, len,
);
- flush_buf(writer, unsafe { DBL_BUFF.cur_ptr() }, len.into());
-
- /*
- uarte
- .0
- .rxd
- .maxcnt
- .write(|w| unsafe { w.maxcnt().bits(BUFLEN as _) });
- */
+ */
+ flush_buf(writer, ptr, len as usize);
} else if uarte.0.events_error.read().events_error().bit_is_set() {
uarte.0.events_error.write(|w| w.events_error().clear_bit());
let len = uarte.0.rxd.amount.read().amount().bits();
- info!("error: {:b} {}b", uarte.0.errorsrc.read().bits(), len,);
+ info!("ERROR {:b} {}b", uarte.0.errorsrc.read().bits(), len);
} else if uarte.0.events_rxto.read().events_rxto().bit_is_set() {
uarte.0.events_rxto.write(|w| w.events_rxto().clear_bit());
let len = uarte.0.rxd.amount.read().amount().bits();
- info!("rxto - {}", len);
- flush_buf(writer, unsafe { DBL_BUFF.cur_ptr() }, len.into());
+ info!("RXTO - {}", len);
+ flush_buf(writer, unsafe { DBL_BUFF.cur_ptr() }, len as usize);
uarte.0.tasks_flushrx.write(|w| w.tasks_flushrx().set_bit());
} else if uarte
.0
@@ -129,7 +113,7 @@ where
.0
.events_rxstarted
.write(|w| w.events_rxstarted().clear_bit());
- info!("rxstarted");
+ //info!("RXSTARTED");
// Swap to the next buffer as soon as the transfer starts to
// try and lose as little data as possible.
@@ -140,7 +124,7 @@ where
fn flush_buf(writer: &mut Writer<u8>, ptr: *mut u8, len: usize) {
let buf = unsafe { core::slice::from_raw_parts(ptr, len) };
- info!("flush start");
+ //info!("flush start");
writer.unshift_from(buf);
- info!("flush end");
+ //info!("flush end");
}