1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
|
use log::info;
use nrf52840_hal::uarte::{self, Uarte};
use starb::{Reader, RingBuffer, Writer};
static mut RB: RingBuffer<u8> = RingBuffer::new(0);
const BUFLEN: usize = 128;
struct DoubleBuffer {
bank0: [u8; BUFLEN],
bank1: [u8; BUFLEN],
is_bank0: bool,
}
impl DoubleBuffer {
const fn new() -> Self {
Self {
bank0: [0; BUFLEN],
bank1: [0; BUFLEN],
is_bank0: true,
}
}
fn cur_ptr(&mut self) -> *mut u8 {
if self.is_bank0 {
self.bank0.as_mut_ptr()
} else {
self.bank1.as_mut_ptr()
}
}
fn next_ptr(&mut self) -> *mut u8 {
self.is_bank0 = !self.is_bank0;
if self.is_bank0 {
self.bank1.as_mut_ptr()
} else {
self.bank0.as_mut_ptr()
}
}
}
static mut DBL_BUFF: DoubleBuffer = DoubleBuffer::new();
pub fn setup<I>(mut uarte: Uarte<I>) -> (Reader<'static, u8>, impl FnMut())
where
I: uarte::Instance,
{
uarte.0.intenset.write(|w| {
w.endrx().set_bit();
w.error().set_bit();
w.rxto().set_bit();
w.rxstarted().set_bit()
});
let ptr = unsafe { DBL_BUFF.next_ptr() };
info!("setting up dma: p: {:x}, maxcnt: {}", ptr as u32, BUFLEN);
uarte.0.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
uarte
.0
.rxd
.maxcnt
.write(|w| unsafe { w.maxcnt().bits(BUFLEN as _) });
uarte.0.tasks_startrx.write(|w| w.tasks_startrx().set_bit());
let (rbr, mut rbw) = unsafe { RB.split() };
// start rx into a buffer. it would be nice if we could do this
// with rxrdy or something like i2c does.
let cl = move || handler(&mut uarte, &mut rbw);
(rbr, cl)
}
fn handler<I>(uarte: &mut Uarte<I>, writer: &mut Writer<u8>)
where
I: uarte::Instance,
{
if uarte.0.events_endrx.read().events_endrx().bit_is_set() {
uarte.0.events_endrx.write(|w| w.events_endrx().clear_bit());
// The buffer should be swapped from the RXSTARTED event, so
// we can restart the read immediately.
let optr = uarte.0.rxd.ptr.read().ptr().bits();
let ptr = unsafe { DBL_BUFF.cur_ptr() as u32 };
/*
if optr == ptr {
uarte
.0
.rxd
.ptr
.write(|w| unsafe { w.ptr().bits(DBL_BUFF.next_ptr() as _) });
}
*/
uarte.0.tasks_startrx.write(|w| w.tasks_startrx().set_bit());
// Copy DMA buffer to ring buffer.
let len = uarte.0.rxd.amount.read().amount().bits();
let mc = uarte.0.rxd.maxcnt.read().maxcnt().bits();
info!(
"endrx - l: {}, p: {:x}, mc: {}, b: {:x}",
len, optr, mc, ptr
);
flush_buf(writer, unsafe { DBL_BUFF.cur_ptr() }, len.into());
/*
uarte
.0
.rxd
.maxcnt
.write(|w| unsafe { w.maxcnt().bits(BUFLEN as _) });
*/
} else if uarte.0.events_error.read().events_error().bit_is_set() {
uarte.0.events_error.write(|w| w.events_error().clear_bit());
let len = uarte.0.rxd.amount.read().amount().bits();
info!("error: {:b} {}b", uarte.0.errorsrc.read().bits(), len,);
} else if uarte.0.events_rxto.read().events_rxto().bit_is_set() {
uarte.0.events_rxto.write(|w| w.events_rxto().clear_bit());
let len = uarte.0.rxd.amount.read().amount().bits();
info!("rxto - {}", len);
flush_buf(writer, unsafe { DBL_BUFF.cur_ptr() }, len.into());
uarte.0.tasks_flushrx.write(|w| w.tasks_flushrx().set_bit());
} else if uarte
.0
.events_rxstarted
.read()
.events_rxstarted()
.bit_is_set()
{
uarte
.0
.events_rxstarted
.write(|w| w.events_rxstarted().clear_bit());
info!("rxstarted");
// Swap to the next buffer as soon as the transfer starts to
// try and lose as little data as possible.
let ptr = unsafe { DBL_BUFF.next_ptr() };
uarte.0.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
}
}
fn flush_buf(writer: &mut Writer<u8>, ptr: *mut u8, len: usize) {
let buf = unsafe { core::slice::from_raw_parts(ptr, len) };
info!("flush start");
writer.unshift_from(buf);
info!("flush end");
}
|
